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CY7C1024DV33
3-Mbit (128K X 24) Static RAM
Features
Functional Description
The CY7C1024DV33 is a high performance CMOS static RAM organized as 128K words by 24 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. To write to the device, enable the chip (CE1 LOW, CE2 HIGH, and CE3 LOW), while forcing the Write Enable (WE) input LOW. To read from the device, enable the chip by taking CE1 LOW, CE2 HIGH, and CE3 LOW while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. See the Truth Table on page 7 for a complete description of Read and Write modes. The 24 I/O pins (I/O0 to I/O23) are placed in a high impedance state when the device is deselected (CE1 HIGH, CE2 LOW, or CE3 HIGH) or when the output enable (OE) is HIGH during a write operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW).
High speed tAA = 10 ns Low active power ICC = 175 mA at 10 ns Low CMOS standby power ISB2 = 25 mA Operating voltages of 3.3 0.3V 2.0V data retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE1, CE2, and CE3 features Available in Pb-free standard 119-ball PBGA

Logic Block Diagram
INPUT BUFFER
ROW DECODER
A(9:0)
128K x 24 ARRAY
SENSE AMPS
I/O0 - I/O23
COLUMN DECODER
CONTROL LOGIC
CE1, CE2, CE3 WE OE
A(16:10)
Cypress Semiconductor Corporation Document Number: 001-08353 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 6, 2008
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CY7C1024DV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 10 175 25 Unit ns mA mA
Pin Configuration
Figure 1. 119-Ball PBGA Top View [1] 1 A B C D E F G H J K L M N P R T U NC NC I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC NC 2 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A 3 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 4 A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A A 6 A A NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A 7 NC NC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 NC I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 NC NC
Note 1. NC pins are not connected on the die.
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
DC Input Voltage [2] ............................... -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND [2] ....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State [2] ................................... -0.5V to VCC + 0.5V
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2
[2]
Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC
Test Conditions [3] VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA
-10 Min 2.4 0.4 2.0 -0.3 -1 -1 VCC + 0.3 0.8 +1 +1 175 30 25 Max
Unit V V V V A A mA mA mA
GND < VOUT < VCC, output disabled VCC = Max, f = fMAX = 1/tRC IOUT = 0 mA CMOS levels
Automatic CE Power Down Max VCC, CE > VIH Current --TTL Inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power Down Max VCC, CE > VCC - 0.3V, Current -- CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board 119-Ball PBGA 20.31 8.35 Unit C/W C/W
Notes 2. VIL (min) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. CE refers to a combination of CE1, CE2, and CE3. CE is LOW when CE1, CE3 are LOW and CE2 is HIGH. CE is HIGH when CE1 is HIGH, or CE2 is LOW, or CE3 is HIGH.
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
Figure 2. AC Test Loads and Waveform[4]
50 OUTPUT Z0 = 50 30 pF* VTH = 1.5V
3.3V OUTPUT 5 pF*
R1 317
R2 351
(a)
*Capacitive Load consists of all components of the test environment
*Including jig
and scope
(b)
All input pulses 3.0V GND 90% 10% (c) 90% 10% Fall Time:> 1V/ns
Rise Time > 1V/ns
AC Switching Characteristics
Over the Operating Range [5] Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE Active LOW to Data Valid [3] OE LOW to Data Valid OE LOW to Low Z
[7] [7] [3, 7]
Description
-10 Min 100 10 10 3 10 5 1 5 3 5 0 Max
Unit
s ns ns ns ns ns ns ns ns ns ns 10 ns
OE HIGH to High Z
CE Active LOW to Low Z
CE Deselect HIGH to High Z [3, 7] CE Active LOW to Power Up [3, 8] CE Deselect HIGH to Power Down
[3, 8]
Notes 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of Figure 2, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured 200 mV from steady state voltage. 8. These parameters are guaranteed by design and are not tested.
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
AC Switching Characteristics
Over the Operating Range [5] Parameter Write Cycle [9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time
(continued)
Description
-10 Min 10 Max
Unit
ns ns ns ns ns ns ns ns ns 5 ns
CE active LOW to Write End Address Setup to Write End
[3]
7 7 0 0 7 5.5 0 3
Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z [7] WE LOW to High Z [7]
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR [11] tR
[12]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions [3] VCC = 2V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V
Min 2
Typ
Max 25
Unit V mA ns ns
0 tRC
Data Retention Waveform
DATA RETENTION MODE
VCC
CE
3.0V tCDR
VDR > 2V
3.0V tR
Notes 9. The internal write time of the memory is defined by the overlap of CE1 and CE2 and CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15]
ADDRESS tRC CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA
Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE transition LOW. 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 18 tHZWE DATA VALID tLZWE tHD tPWE tHA
Truth Table
CE1 H X X L L L CE2 X L X H H H CE3 X X H L L L OE X X X L X H WE X X X H L H High Z High Z High Z Full Data Out Full Data In High Z I/O0 - I/O23 Mode Power Down Power Down Power Down Read Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC)
Selected, Outputs Disabled Active (ICC)
Note 18. During this period, the I/Os are in the output state and input signals are not applied.
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
Ordering Information
Speed (ns) 10 Ordering Code CY7C1024DV33-10BGXI Package Name 51-85115 Package Type 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Operating Range Industrial
Package Diagram
Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm)
51-85115-*B
Document Number: 001-08353 Rev. *C
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CY7C1024DV33
Document History Page
Document Title: CY7C1024DV33, 3-Mbit (128K X 24) Static RAM Document Number: 001-08353 Rev. ** *A ECN No. 469517 499604 Orig. of Change NXR NXR Submission Date See ECN See ECN New data sheet Added note 1 for NC pins Changed ICC specification from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table on page 4 Converted from preliminary to final Updated block diagram Changed ICC specification from 185 mA to 225 mA Updated thermal specs Removed Commercial operating range, Added Industrial operating range Removed 8 ns speed bin, Added 10 ns speed bin Description of Change
*B
1462586
VKN/SFV
See ECN
*C
2604677
VKN/PYRS
11/12/08
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(c) Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08353 Rev. *C
Revised November 6, 2008
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